1. Field of the Invention
Apparatuses consistent with the present invention relate to a digital frequency detector and a digital phase locked loop (PLL) using the digital frequency detector. More particularly, apparatuses consistent with the present invention relate to a digital frequency detector for use in a digital PLL or a frequency synthesizer, and a digital PLL using the digital frequency detector.
2. Description of the Related Art
Generally, a PLL is used to obtain an output signal having a fixed phase and frequency by sensing and controlling the change of the phase and frequency that may occur in peripheral environments.
FIG. 1 is a block diagram schematically illustrating the construction of a related PLL.
Referring to FIG. 1, a PLL comprises a phase frequency detector (PFD) 10, a charge pump 30, a loop filter 50, a voltage controlled oscillator (VCO) 70, and a divider 90.
The PFD 10 compares an input frequency Fcc with a frequency output from the divider 90 to be described later, and outputs a pulse string corresponding to a difference between the two frequencies.
The charge pump 30 pushes or pulls current that is in proportion to a width of the pulse output from the PFD 10 in accordance with a pulse code. In the process of converting the pulse into the current as described above, a current gain is produced to exert a great influence upon the performance of the PLL including a lock time for which the output of the PLL is stabilized.
The loop filter 50 has a structure of a low pass filter, and filters noise generated during the operation of the loop. The loop filter 50 varies the voltage of a control terminal of the VCO 70 by changing the amount of charge accumulated using capacitors.
The VCO 70 outputs a specified frequency Fvco, which is a high frequency, in accordance with the voltage output from the loop filter 50.
The divider 90 divides the output frequency Fvco of the VCO 70 to output a frequency that comparable with the input frequency Fcc provided to the PFD 10.
As described above, the PLL is a circuit that processes the frequency in an analog form, and an analog type circuit has a high sensitivity to external noise if the supply voltage is reduced. According to recent semiconductor processes, there is a growing tendency that a speed of a transistor is increased while a supply voltage is reduced, and due to this, circuits, which had been designed in an analog domain, are now being designed in a digital domain.
The tendency also appears in the field of PLLs. In implementing a digital PLL, the biggest problem is that the accuracy of the digital PLL is lowered in the case of converting the high frequency signal output from the VCO into a digital signal. The problem occurs not only in the digital PLL but also in a frequency synthesizer and the like, designed in the digital domain.